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adc wit h microphone input and programmable digital filters http://www.cirrus.com copyright ? cirrus logic, inc., 20 05 C 201 6 (all rights reserved) rev 4. 5 aug 1 6 wm 8950 description the WM8950 is a low power, high quality mono adc designed for portable applications such as digital s till c amera , digital voice recorder or games console accessories . the device integrates sup port for a differential or single ended mic . externa l component requirements are reduced as no separate microphone amplifiers are required. advanced sigma delta converters are used along with digital decimation filters to give high quality audio at sample rates from 8 to 48ks/s . additional digital filterin g options are available, to cater for application filtering suc h as wind noise reduction, noise rejection , plus an advanced mixed signal alc function with noise gate is provided. an on - chip pll is provided to generate the required master clock from an exte rnal reference clock . the pll clock can also be output if required elsewhere in the system. the WM8950 operates at supply voltage s f rom 2.5 to 3.6 v, although the digital supplies can operate at voltages down to 1. 71v to save power. different sections of t he chip can also be powe red down under software control by way of the selectable two or three wire control interface. WM8950 is supplied in a very small 4x4 mm qfn package, offering high levels of functionality in minimum board area, with high thermal perfo rmance. features mono adc : ? audio sample rates: 8, 11.0 25, 16, 22.05, 24, 32, 44.1, 48khz ? snr 9 4 db, thd - 8 3 db (a - weighted @ 8 C 48ks/s) ? multiple auxiliary analog ue input s mic preamps : ? differential or single end microphone interface - programmable preamp gai n - pse u do differential inputs with common mode rejection - programmable alc / noise gate in adc path ? low - noise bias supplied for electret microphones other features ? 5 band eq ? programmable high - pass filter ( wind noise reduction ) ? fully programmable iir filter ( notch filter) ? on - chip pll ? low power, low voltage - 2.5 v to 3.6v (digita l : 1. 71v to 3.6v) - power consumption 10ma all - on 48ks/s mode ? 4 x 4 x0.9mm 24 lead qfn package a pplications ? digital still camera ? general purpose low power audio adc ? games console accessories ? v oice recorders c o n t r o l i n t e r f a c e c s b / g p i o s d i n s c l k m i c b i a s w m 8 9 5 0 d g n d a v d d a g n d v m i d 5 0 0 k 5 0 0 k i 2 s o r p c m i n t e r f a c e a d c a d c d i g i t a l f i l t e r s p l l 5 0 k 5 0 k 4 k 5 k m c l k d b v d d a v d d 2 a g n d 2 a u x 2 0 k 2 0 k a n a l o g i n p u t s r b i a s m i c n o i s y g n d g a i n s : - 1 2 d b t o + 3 5 . 2 5 d b d c v d d m o d e m i c n m i c p i p p g a i p b o o s t / m i x f r a m e a d c d a t t p b c l k a u t o m a t i c l e v e l c o n t r o l 5 b a n d e q p r o g r a m m a b l e h i g h p a s s f i l t e r i i r f i l t e r w i t h p r o g r a m m a b l e c o e f f i c i e n t s d s p c o r e
WM8950 2 rev 4.5 table of contents description ................................ ................................ ................................ ....... 1 features ................................ ................................ ................................ ............ 1 applications ................................ ................................ ................................ ..... 1 table of contents ................................ ................................ ......................... 2 pin configuration ................................ ................................ .......................... 3 ordering information ................................ ................................ .................. 3 pin description ................................ ................................ ................................ 4 absolute maximum rat ings ................................ ................................ ........ 5 recommended operatin g conditions ................................ ..................... 5 electrical character istics ................................ ................................ ..... 6 terminology ................................ ................................ ................................ ............... 7 signal timing requir ements ................................ ................................ ...... 8 system clock timing ................................ ................................ ................................ 8 audio interface timi ng C master mode ................................ ............................ 8 audio interface timi ng C slave mode ................................ ................................ 9 control interface ti ming C 3 - wire mode ................................ ....................... 10 control interface ti ming C 2 - wire mode ................................ ....................... 11 device description ................................ ................................ ...................... 12 introduction ................................ ................................ ................................ ............ 12 input signal path ................................ ................................ ................................ .... 13 analogue to digital converter (adc) ................................ ............................ 18 input automatic leve l control (alc) ................................ ............................. 22 digital audio interf aces ................................ ................................ ..................... 36 audio sample rates ................................ ................................ ................................ 41 master clock and pha se locked loop (pll) ................................ ................. 42 general purpose inpu t/output ................................ ................................ ........ 44 control interface ................................ ................................ ................................ . 44 resetting the chip ................................ ................................ ................................ . 45 power supplies ................................ ................................ ................................ ....... 46 adc power up/down se quence ................................ ................................ .......... 46 power management ................................ ................................ ............................... 47 register map ................................ ................................ ................................ .. 49 digital filter chara cteristics ................................ .............................. 50 terminology ................................ ................................ ................................ ............. 50 adc filter responses ................................ ................................ ........................... 50 de - emphasis filter resp onses ................................ ................................ .......... 51 high - pass filter ................................ ................................ ................................ ...... 52 5 - band equaliser ................................ ................................ ................................ ..... 53 applications informa tion ................................ ................................ ........ 57 recommended external components ................................ ............................ 57 package diagram ................................ ................................ ......................... 58 important notice ................................ ................................ ......................... 59 revision history ................................ ................................ ........................... 60
WM8950 rev 4.5 3 pin configuration ordering information order code temperat ure range package moisture sensitivity level package body temperature WM8950 c gefl/v - 40 ? c to +85 ? c 24 - lead qfn (4x4x0.9mm) ( pb - free ) msl3 260 o c WM8950 c gefl/rv - 40 ? c to +85 ? c 24 - lead qfn (4x4x0.9mm) (pb - free , tape and reel) msl3 260 o c note: reel quant ity = 3,500 m c l k m o d e f r a m e b c l k t p a d c d a t 1 2 3 4 5 6 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 1 9 2 0 2 1 2 2 2 3 2 4 w m 8 9 5 0 ( t o p v i e w ) d n c v m i d a v d d 2 a u x m i c n m i c p a v d d a g n d d g n d d c v d d d b v d d m i c b i a s a g n d 2 d n c s c l k c s b / g p i o s d i n d n c
WM8950 4 rev 4.5 pin description pin no name type description 1 micbias analogue output microphone bias 2 avdd supply analogue supply (feeds adc) 3 agnd supply analogue ground (feeds adc) 4 dcvdd supply digital core supply 5 dbvdd supply digital buffer ( input / output ) supply 6 dgnd supply digital ground 7 adcdat digital output adc digital audio data output 8 tp test pin connect to ground 9 frame digital input / output adc sample rate clock or frame synch 10 bclk digital input / output digital audio bit clock 11 mclk digital input master c lock input 12 csb/gpio digital input / output 3 - wire mpu chip select or general purpose input / output pin. 13 sclk digital input 3 - wire mpu clock input / 2 - wire mpu clock input 14 sdin digital input / output 3 - wi re mpu data input / 2 - wire mpu data input 15 mode digital input control interface mode selection pin . 16 dnc do not connect leave this pin floating 17 dnc do not connect leave this pin floating 18 a gnd 2 supply analogue ground 19 dnc do not connect le ave this pin floating 20 a vdd 2 supply analogue supply 21 aux analogue input auxiliary analogue input 22 vmid reference decoupling for midrail reference voltage 23 micn analogue input microphone negative input 24 micp analogue input microphone positive input (common mode) note: it is recommended that the qfn ground paddle should be connected to analogue ground on the application pcb.
WM8950 rev 4.5 5 absolute maximum rat ings absolute maximum ratings are stress ratings only. permanent damage to the device may be cause d by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of t his device. cirrus logic tests its package types according to ipc/jedec j - std - 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? ? ? condition min max dbvdd, dcvdd, avdd , avdd2 supply voltages - 0.3v + 4.2 voltage range digital inputs dgnd - 0.3v dvdd +0.3v voltage range analogue input s agnd - 0.3v avdd +0.3v operating temperature range, t a - 40 ? ? ? ? ? notes : 1. analogue and digital grounds must always be within 0.3v of each oth er. 2. all digital and analogue supplies are completely independent from each other. recommended operatin g conditions parameter symbol min typ max unit digital supply range (core) dcv dd 1.71 3.6 v digital supply range (buffer) dbvdd 1.71 3.6 v analogue supplies range av dd, avdd2 2.5 3.6 v ground dgnd, agnd, agnd2 0 v notes : 1. when using pll, dcvdd must be 1.9v or higher. 2. avdd must be ? dbvdd and dcvdd. 3. dbvdd must be ? dcvdd. 4. when using pll, dcvdd must be ? 1.9v.
WM8950 6 rev 4.5 electrical character istics test condit ions d c v dd = 1. 8 v , avdd = db vdd = 3.3 v, spkvdd = 3.3v, t a = +25 o c, 1khz signal, fs = 48khz, 24 - bit audio data unless otherwise stated. parameter symbol test conditions min typ max unit microphone inputs ( micn , micp ) ful l - scale input signal level (note 1) C note this changes with avdd v infs pgaboost = 0db inppgavol = 0db 1.0 0 vrms dbv mic pga equivalent input noise at 35.25 db gain 150 uv input resistance r micin gain set to 35.25db 1 .6 k ? input resistance r micin gain set to 0db 47 k ? input resistance r micin gain set to - 12db 75 k ? input resistance r mici p (constant for all gain settings) 94 k ? input capacitance c micin 10 pf mic input programmable gain amplifier (pga) maximum programmable gain 35.25 db minimum programmable g ain - 12 db programmable gain step size guaranteed monotonic 0.75 db mute attenuation 108 db selectable input gain boost (0/+20db) gain boost 0 20 db automatic level control (alc)/limiter target record level - 28.5 - 6 db maximum progr ammable gain 35.25 db minimum programmable gain - 12 db programmable gain step size guaranteed monotonic 0.75 db gain hold time (note 2 ) t hold mclk=12.288mhz (note 4 ) 0, 2.67, 5.33, 10.67, , 43691 (time doubles with each step) ms gain ramp - up (decay) time (note 3 ) t dcy alcmode=0 (alc), mclk=12.288mhz (note 4 ) 3.3, 6.6, 13.1, , 3360 (time doubles with each step) ms alcmode=1 (limiter), mclk=12.288mhz (note 4 ) 0.73, 1.45, 2.91, , 744 (time doubles with each step) gain ramp - down (attac k) time (note 3 ) t atk alcmode=0 (alc), mclk=12.288mhz (note 4 ) 0.83, 1.66, 3.33, , 852 (time doubles with each step) ms alcmode=1 (limiter), mclk=12.288mhz (note 4 ) 0.18, 0.36, 0.73, , 186 (time doubles with each step) analogue to digital converte r (adc) signal to noise ratio (note 5 , 6 ) a - weighted, 0db pga gain 85 9 4 db total harmonic distortion + noise (note 6 ) thd+n - 1 db fs input 0db pga gain - 75 - 8 3 db auxiliary analogue input (aux) full - scale input signal level (0db) C note this changes with avdd v infs 1.0 0 vrms dbv input resistance r auxin auxmode=0 20 k ? input capacitance c auxin 10 pf
WM8950 rev 4.5 7 test conditions dcvdd = 1. 8 v, avdd = dbvdd = 3.3v, spkvdd = 3.3v, t a = +25 o c, 1khz si gnal, fs = 48khz, 24 - bit audio data unless otherwise sta ted. parameter symbol test conditions min typ max unit microphone bias bias voltage (mbvsel=0) v micbias 0.9 x avdd v bias voltage (mbvsel=1) v micbias 0.75 x avdd v bias current source i micbias 3 ma output noise voltage vn 1k to 20khz 15 nv/ ? digital input / output input high level v ih 0.7 ? il 0.3 ? oh i ol =1ma 0.9 ? ol i oh - 1ma 0.1 x dvdd v terminology 1. micn input only in single ended microphone configuration. maximum input signal to micp without distortion is - 3dbv. 2. hold time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. it does not apply to ramping down the gain when the signal is too loud, which happens without a delay. 3. ramp - up and ramp - down times are defined as the time it takes for the pga to change it s gain by 6db . 4. all hold, ramp - up and ramp - down times scale proportionally with mclk 5. signal - to - noise ratio (db) C snr is a measure of the di fference in level between the full scale output and the output with no signal applied. (no auto - zero or automute function is employed in achieving these results). 6. thd+n (db) C thd+n is a ratio, of the rms values, of (noise + distortion)/signal.
WM8950 8 rev 4.5 s ignal t im ing r equirements s ystem c lock t iming figure 1 system clock timing requirements test conditions dcvdd=1.8v, dbvdd=avdd=spkvdd=3.3v, dgnd=agnd=spkgnd=0v, t a = +25 o c , slave mode fs = 48khz , mclk = 256fs, 24 - bit data, unless other wise stated. parameter symbol conditions min typ max unit system clock timing information mclk cycle time t mclky mclk as direct sysclk source (clksel=0) 81.38 ns mclk as input to pll (see note) ( clksel=1 ) 20 ns mclk duty cycle t mclkds 60:40 40:60 note: pll pre - scaling and pll n and k values should be set appropriately so that sysclk is no greater than 12.288mhz. a udio interface timing C m aster m ode figure 2 digital audio data timing C master mode (see control interface) test conditions dcvdd= 1. 8 v , dbvdd=avdd=spkvdd=3.3v, dgnd=agnd =spkgnd =0v, t a = +25 o c, master mode, fs=48khz, mclk=256fs, 24 - bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing in formation frame propagation delay from bclk falling edge t dl 10 ns adcdat propagation delay from bclk f alling edge t dda 10 ns mclk t mclkl t mclkh t mclky b c l k ( o u t p u t ) a d c d a t f r a m e ( o u t p u t ) t d l t d d a
WM8950 rev 4.5 9 a udio i nterface t iming C slave m ode figure 3 digital audio data timing C slave mode test conditions dcvdd= 1. 8 v , dbvdd=avdd =spkvdd=3.3v, dgnd=agnd= spkgnd =0v, t a =+25 o c, slave mode, fs= 48khz, mclk= 256fs, 24 - bit data, unless otherwise stated. parameter symbol min typ max unit audio data input timing information bc lk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns frame set - up time to bclk rising edge t lrsu 10 ns frame hold time from bclk rising edge t lrh 10 n s adcdat propagation delay from bclk falling edge t dd 20 ns note: bclk period should always be greater than or equal to mclk period. b c l k f r a m e t b c h t b c l t b c y a d c d a t t l r s u t l r h t d d
WM8950 10 rev 4.5 control i nterface t iming C 3 - wire m ode figure 4 control interface timing C 3 - wire serial control mode test conditions dcvdd = 1. 8 v , dbvdd = avdd = spkvdd = 3.3v, dgnd = agnd = spk gnd = 0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24 - bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk rising edge to csb r ising edge t scs 80 ns sclk pulse cycle time t scy 200 ns sclk pulse width low t scl 80 ns sclk pulse width high t sch 80 ns sdin to sclk set - up time t dsu 40 ns sclk to sdin hold time t dho 40 ns csb pulse width low t csl 40 ns csb pulse wid th high t csh 40 ns csb rising to sclk rising t css 40 ns pulse width of spikes that will be suppressed t ps 0 5 ns c s b / g p i o s c l k s d i n t c s l t d h o t d s u t c s h t s c y t s c h t s c l t s c s l s b t c s s
WM8950 rev 4.5 11 control i nterface t iming C 2 - wire m ode figure 5 control interface timing C 2 - wire serial control mode tes t conditions dcvdd= 1.8 v , dbvdd=avdd=spkvdd=3.3v, dgnd=agnd =spkgnd =0v, t a = +25 o c, slave mode, fs = 48khz, mclk = 256fs, 24 - bit data, unless otherwise stated. parameter symbol min typ max unit program register input information sclk frequency 0 526 khz sclk low pulse - width t 1 1.3 us sclk high pulse - width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sdin, sclk rise time t 6 300 ns sdin, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns sdin sclk t 3 t 1 t 6 t 2 t 7 t 5 t 4 t 3 t 8 t 9
WM8950 12 rev 4.5 d evice d escription i ntroduction the WM8950 is a low power audio adc , with flexible line and microphone input . applications for this device include games console accessories , digital still cameras, voice recorders and other general purpose audio applications . the chip offers great flexibility in use, and so can support many different modes of operation as follows: microphone inputs m ic rophone inputs are provided, allowing for either a differential microphone input or a single ended microphone to be connected. these inputs have a use r programmable gain range of - 12db to +35.25 db using internal resistors . after the input pga stage comes a boost stage which can add a further 20db of gain. a microphone bias is output from the chip which can be used to bias the microphones. the signal routing can be configured to allow manual adjustment of mic levels, or to allow the alc loop to control th e level of mic signal that is transmitted. t otal gain through the microphone paths of up to + 55.25 db can be selected. pga and alc operatio n a programmable gain amplifier is provided in the input path to the adc. this may be used manually or in conjunction with a mixed analog ue /digital automatic level control (alc) which keeps the recording volu me constant. aux input the device includes a mono input, aux, that can be used as an input for warning tones ( beep ) etc. this path can also be summed into the input i n a flexible fashio n , either to the input pga as a second microphone input or as a line input. the configuration of this circuit , with integrated on - chip resistors allows several analogue signals to be summed into the single aux input if required. adc the mono adc uses a multi - bit high - order oversampling architecture to deliver optimum performance with low power consumption. various sample rates are supported, from the 8ks/s rate typically used in voice dictation , up to the 48ks/s rate used in high quality audio applications. digital filtering advanced sigma delta converters are used along with digital decimation and interpolation filters to give high quality audio at sample rates from 8 ks/s to 48ks/s. application specific digital filters are also available which help to re duce the effect of specific noise sources such as wind noise . the filters include a programmable adc high - pass filter, a n iir filter with fully programmable coefficients, and a 5 - band equaliser that can be applied to the record path in order to improve the overall audio sound from the device. audio interfaces the WM8950 has a standard audio interface, to support the transmission of audio data from the chip. this interface is a 4 wire standard audio interface which supports a number of au dio data formats including i 2 s, dsp mode, msb - first, left justified and msb - first, right justified, and can oper ate in master or slave modes. control interfaces to allow full software control over all its features, the WM8950 offers a choice of 2 or 3 wire mpu control interface. it is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and dsps . the selection between 2 - wire mode and 3 - wire mode is determined by the state of the mode pin . if mode is high then 3 - wire control mode is selected, if mode is low then 2 - wire control mode is selected . i n 2 wire mode, only slave operation is supported, and the address of the device is fixed as 0011010 . clocking schemes WM8950 offers the normal audio clock ing sche me operation, where 256fs mclk is provided to the adc .
WM8950 rev 4.5 13 however, a pll is also included which may be used to generate the internal master clock frequency in the event that this is not available from the system controller. th e pll uses an input reference ( ty pically , the 12mhz usb clock ) to gen erate high quality audio clocks . if th e pll is not required for generation of these clocks, it can be reconfigured to generate alternative clocks which may then be output on the csb /gpio pin and used elsewhere in the sys tem. power control the design of the WM8950 has given much attention to power consumption without compromising performance. it operates at low supply voltages, and includes the facility to power off any unused parts of the circuitry under software control, includes standby and power off modes. input signal path the WM8950 has 3 flexible analogue inputs: two microphone inputs, and an auxiliary input . these inputs can be used in a variety of ways. the input signal path before the adc has a flexible pga blo ck which then feeds into a gain boost/mixer stage. microphone inputs the WM8950 can accommodate a variety of microphone configurations includi n g single ended and differential inputs. the inputs through the micn, micp and optionally aux pins are amplified through the input pga as shown in figure 6 . a pseudo differential input is the preferential configuration where the positive terminal of the input pga is connected to the micp input pin by setting micp2inppga=1. the microphone g round should then be connected to micn (when micn2inppga=1) or optionally to aux (when aux2inppga=1) input pins. alternatively a single ended microphone can be connected to the micn input with micn2inppga set to 1. the non - inverting terminal of the input pga should be connected internally to vmid by setting micp2inppga to 0. figure 6 microphone input pga circuit (switch positions shown are for differential mic input) o u t p u t f r o m a u x a m p m i c p m i c n v m i d a u x 2 i n p p g a r 4 4 [ 2 ] m i c n 2 i n p p g a r 4 4 [ 1 ] m i c p 2 i n p p g a r 4 4 [ 0 ] t o i n p u t b o o s t / m i x s t a g e i n p p g a v o l r 4 5 [ 5 : 0 ] g a i n = - 1 2 t o + 3 5 . 2 5 d b
WM8950 14 rev 4.5 register address bit label default description r44 input control 0 micp2inppga 1 connect input pga amplifier positive terminal to micp or vmid. 0 = input pga amplifier posi tive terminal connected to vmid 1 = input pga amplifier positive terminal connected to micp through variable resist or string 1 micn2inppga 1 connect micn to input pga negative terminal . 0=micn not connected to input pga 1=micn connected to input pga amplifier negative terminal. 2 aux2inppga 0 select aux amplifier output as input pga signal source. 0=aux not connected to input pga 1=aux connected to input pga amplifier negative terminal. the input pga is enabled by the ippgaen register bit . register address bit label default description r2 power management 2 2 inppga en 0 input microphone pga enable 0 = disabled 1 = enabled input pga volume control the input microphone pga has a gain range from - 12db to +35.25db in 0.75db steps . the gain from the micn input to the pga output and from the aux amplifier to the pga output are always common and controlled by the regist er bits inppgavol[5:0]. these register bits also a ffect the micp pin when micp2inppga =1. when the automatic level control (alc) is enabled t he input pga gain is then controlled automatically and the inppgavol bits should not be used. register address bi t label default description r45 input pga volume control 5:0 inppga vol 010000 input pga volume 000000 = - 12db 000001 = - 11.25d b . 010000 = 0db . 111111 = 35.25db 6 inppgamute 0 mute control for input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). 7 inppga zc 0 input pga zero cross enable: 0=update gain when gain register changes 1=update gain on 1 st zero cross after gain register write.
WM8950 rev 4.5 15 register address bi t label default description r 3 2 alc control 1 8 alcsel 0 alc function s elect: 0=alc off (pga gain set by inp p gavol register bits) 1=alc on (alc controls pga gain) table 1 input pga volume control auxiliary input an auxiliary input circuit ( figure 7 ) is provided which consists of an a mplifier which can be configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple inputs with the use of external resistors. the ci rcuit is enabled by the register bit auxen . figure 7 auxi liary i nput c ircuit the auxmode register bit controls the aux i l i ary input mode of operation: i n buffer mode (auxmode=0) the switch labelled auxsw in figure 7 is open and the signal at the aux pin will be buffered and inverted through the aux circuit using only the internal components. in mixer mode (auxmode=1) the on - chip input resistor is bypassed, this allows the user to sum in mult iple inputs with the use of external resistors. when used i n this mode there will be gain variations through this pat h from part to part due to the variation of the internal 20k ? resistors relative to the higher tolerance external resistors . register address bit label default description r 1 power management 1 6 auxen 0 auxi liary input buffer enable 0 = off 1 = on r 4 4 input control 3 auxmode 0 0 = inverting buffer 1 = mixer (on - chip input resistor bypassed) table 2 auxi liary i nput b uffer c ontrol - + v m i d a u x 2 0 k 2 0 k a u x s w c l o s e d w h e n s u m m i n g m u l t i p l e i n p u t s t o i n p p g a , i n p b o o s t o r o u t p u t m i x e r s a u x m o d e r 4 4 [ 3 ] a u x s w a u x o p
WM8950 16 rev 4.5 input boost the input boost circuit has 3 selectable inputs: the input microphone pga output , the aux amplifier output and the micp input pin (when not using a differential microphone configuration). these three inputs can be mixed together and have individual gain boost/adjust as shown in figure 8 . figure 8 input boost stage the input pga path can h ave a +20db boost (pgaboost=1) a 0db pass through (pgaboost=0) or be completely isolated from the input boost circuit (inppgamute=1). register address bit label default description r 45 input pga gain control 6 inppgamute 0 mute control for input pga: 0=input pga not muted, normal operation 1=input pga muted (and disconnected from the following input boost stage). r47 input boost control 8 pgaboost 1 0 = pga output has +0db gain through input boost stage. 1 = pga output has +20db gain thr ough input boost stage. table 3 input boost s tage c ontrol the auxi liary amplifier path to the boost stage is controlled by the aux2boost vol [2:0] register bits. when aux2boost vol =000 this path is completely disconnected from the boost stage. settings 001 through to 111 control the gain in 3db steps from - 12db to +6db. the micp path to the boost stage is controlled by the micp2boost vol [2:0] register bits. when micp2boost vol =000 this input pin is completely disconnected from the b oost stage. settings 001 through to 111 control the gain in 3db steps from - 12db to +6db. t o a d c i n p u t a n d o u t p u t m i x e r s a u x 2 b o o s t v o l = 0 0 0 m i c p 2 b o o s t v o l = 0 0 0 o u t p u t f r o m a u x a m p o u t p u t f r o m i n p u t p g a m i c p a u x 2 b o o s t v o l r 4 7 [ 2 : 0 ] m i c p 2 b o o s t v o l r 4 7 [ 6 : 4 ] i n p p g a m u t e r 4 5 [ 6 ] p g a b o o s t r 4 7 [ 8 ] - 1 2 d b t o + 6 d b - 1 2 d b t o + 6 d b 0 d b o r + 2 0 d b
WM8950 rev 4.5 17 register address bit label default description r47 input boost control 2:0 aux2boostvol 000 controls the auxiliary amplif i er to the input boost stage: 000=path disa bled (disconnected) 001= - 12db gain through boost stage 010= - 9db gain through boost stage table 4 input boost s tage c ontrol the boost stage is enabled under control of the boosten register bit. register address bit label default description r2 power management 2 4 boosten 0 input boost enable 0 = boost stage off 1 = boost stage on table 5 input boost e nable c ontrol microphone biasing c ircuit the micbias output provide s a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. refer to the applications information section for recommended external components. the micbias voltage can be altered via t he mbvsel register bit. if mbvsel = 0, the micbias voltage is 0.9 x avd d . if mbvsel = 1, the micbias voltage is 0.75 x avdd. the output can be enabled or disabled using micb en. register address bit label default description r1 power management 1 4 micb en 0 microphone bias enable 0 = off (high impedance output) 1 = on table 6 microphone bias enable register address bit label default description r44 input control 8 mbvsel 0 microphone bias voltage control 0 = 0.9 x avdd 1 = 0.75 x avdd table 7 microphone bias voltage control the internal micbias circuitry is shown in figure 9 . note that the maximum source current capability for micbias is 3ma. the external biasing resisto rs therefore must be large enough to limit the micbias current to 3ma.
WM8950 18 rev 4.5 figure 9 microphone bias schematic a nalogue t o d igital c onverter ( adc ) the WM8950 uses a multi - bit, oversampled sigma - delta adc channel. the use of multi - bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. the adc full scale input level is proportional to avdd. with a 3.3v supply voltage, the full scale level is 1.0 v rms . any voltage greater than - 1dbfs may overload the adc and cause distortion. adc digital filter s the adc filters perform true 24 bit signal processing to convert the raw multi - bit oversampled data from the adc to the correct sampling frequency to be output on the digital audio interface. the digit al filter path is illustrated in figure 10 . figure 10 adc digital filter path the adc is ena bled by the adcen register bit. register address bit label default description r2 power management 2 0 adcen 0 0 = adc disabled 1 = adc enabled table 8 adc enable a g n d m b v s e l = 0 m i c b i a s = 1 . 8 x v m i d = 0 . 9 x a v d d v m i d i n t e r n a l r e s i s t o r i n t e r n a l r e s i s t o r m b m b v s e l = 1 m i c b i a s = 1 . 5 x v m i d = 0 . 7 5 x a v d d a d c d i g i t a l d e c i m a t o r d i g i t a l f i l t e r s g a i n 5 - b a n d e q u a l i s e r h i g h p a s s f i l t e r i i r f i l t e r d i g i t a l a u d i o i n t e r f a c e a d c d i g i t a l f i l t e r s
WM8950 rev 4.5 19 the polarity of the output signal can also be changed under software control using the adcpol register bit . the oversampling rate of the adc can be adjusted using the adcosr register bit. with adcosr=0 the oversample rate is 64x which gives lowest power operation and when adcosr=1 the overs ample rate is 128x which gives best performance. register address bit label default description r14 adc control 3 adcosr 0 adc oversample rate select: 0=64 x (lower power) 1=128 x (best performance) 0 adcpol 0 0=normal 1=inverted table 9 adc oversample rate select selectable high - pass filter a selectable high - pass filter is provided. to disable this filter set hpfen=0 . th e filter has two modes controlled by hpfapp . in audio mode (hpfapp=0) the filter is first order, with a cu t - off frequency of 3.7hz. in application mode (hpfapp=1) the filter is second order, with a cut - off frequency selectable via the hpfcut register. the cut - off f requencies when hpfapp=1 are shown in table 11 . register address bit lab el default description r14 adc control 8 hpfen 1 high - pass filter enable 0=disabled 1=enabled 7 hpfapp 0 select audio mode or application mode 0=audio mode (1 st order, fc = ~3.7hz) 1=application mode (2 nd order, fc = hpfcut) 6:4 hpfcut 0 00 applicati on mode cut - off frequency see table 11 for details. table 10 adc filter select hpfcut [2:0] sample frequency ( k h z ) 8 11.025 12 16 22.05 24 32 44.1 48 sr=101/100 sr=011/010 sr=001/000 000 82 113 122 8 2 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 196 131 180 196 131 180 196 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 3 27 450 490 111 408 563 612 408 563 612 408 563 612 table 11 high - pass filter cut - off frequencies (hpfapp=1) values in hz note that th e high - pass filter values (when hpfapp=1) work on the basis that the sr register bits are set c orrectly for the actual sample rate as shown in table 11 .
WM8950 20 rev 4.5 programmable iir filter a n iir filter with fully programmable coefficients is provided , typically used as a notch filter for removing narrow band noise at a given frequency . this notch filter has a variable centre frequency and bandwidth, programmable via two coefficients, a0 and a1. these coefficients should be converted to 2s complement numbers to determine the register values. a0 and a1 are represented by the register bi ts nfa0[13:0] and nfa1[13:0]. because these coefficient values require four register writes to setup there is an nfu (notch filter update) flag which should be set only when all four registers are setup. register address bit label default description r27 notch filter 1 6:0 nfa0[13:7 ] 0 notch filter a0 coefficient, b its [13:7 ] 7 nfen 0 notch filter enable: 0=disabled 1=enabled 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. r28 no tch filter 2 6:0 nfa0 [6:0] 0 notch filter a0 coefficient, bits [ 6:0 ] 8 nfu ] 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. r29 notch filter 3 6:0 nfa1[13:7 ] 0 notch filter a1 coefficie nt, bits [13:7 ] 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. r30 notch filter 4 6:0 nfa1[6:0 ] 0 notch filter a1 coefficient, bits [6:0 ] 8 nfu 0 notch filter update. the notch filter values used internally only update when one of the nfu bits is set high. table 12 notch filter function the coefficients are calculated as follows: w here : f c = centre frequency in hz, f b = - 3db bandwidth in hz, f s = sample frequency in hz the coefficients are calculated as follows: nfa0 = - a0 x 2 13 nfa1 = - a1 x 2 12 these values are then converted to 2s compl e ment notation to determine the register values. ) 2 / tan( 1 ) 2 / tan( 1 0 b b w w a ? ? ? ) cos( ) 1 ( 0 0 1 w a a ? ? ? s c f f w / 2 0 ? ? s b b f f w / 2 ? ?
WM8950 rev 4.5 21 notch filter worked example the following example illustrates how to calculate the a0 and a1 coefficients for a desired centre frequency and - 3db bandwidth. fc = 1000 hz fb = 100 hz fs = 48000 hz = x (1000 / 48000) = 0.1308996939 rads = x (100 / 48000) = 0.01308996939 rads = = 0.9869949627 = = - 1.969995945 nfn_a0 = - a0 x 213 = - 8085 (rounded to nearest whole number) nfn_a1 = - a1 x 212 = 8069 (rounded to nearest whole number) these values are then converted to 2s compl e ment: nfa0 = 14h 206b = 14b 10000001101011 nfa1 = 14h 1f85 = 14b 01111110000101 digital adc volume c ontrol the output of the adcs can be digitally attenuated over a range from C 127db to 0db in 0.5db steps. the gain for a given eight - bit code x is given by: gain = 0.5 x ( x C 255) db for 1 ? x ? 255, mute for x = 0 register address bit label default description r15 adc digital volume 7:0 adcvol [7:0] 11 1111 11 ( 0db ) adc digital volume control 0000 0000 = digital mute 0000 0001 = - 127db 0000 001 0 = - 126.5db ... 0.5db steps up to 1111 1111 = 0db table 13 adc volume s c 0 f / f 2 w ? ? ? 2 s b b f / f 2 w ? ? ? 2 ) 2 / w tan( 1 ) 2 / w tan( 1 a b b 0 ? ? ? ) 2 / 9 0130899693 . 0 tan( 1 ) 2 / 9 0130899693 . 0 tan( 1 ? ? ) w cos( ) a 1 ( a 0 0 1 ? ? ? ) 1308996939 . 0 cos( ) 9869949627 . 0 1 ( ? ?
WM8950 22 rev 4.5 input automatic leve l control (alc) the WM8950 has an automatic pga gain control circuit, which can function as an input peak limiter or as an automatic level control (alc). the automatic level control (alc) provides continuous adjustment of the input pga in response to the amplitude of the input signal. a digital peak detector monitors the input signal amplitude and compares it to a register defined threshol d level (alclvl). if the signal is below the threshold, the alc will increase the gain of the pga at a rate set by alcdcy. if the signal is above the threshold, the alc will reduce the gain of the pga at a rate set by alcatk. the alc has two modes selec ted by the alcmode register: normal mode and peak limiter mode. the alc/limiter function is enabled by setting the register bit r32[8] alcsel. register address bit label default description r32 (20h) alc control 1 2:0 alcmin [2:0] 000 ( - 12db) set minimum gain of pga 000 = - 12db 001 = - 6db 010 = 0db 011 = +6db 100 = +12db 101 = +18db 110 = +24db 111 = +30db 5:3 alcmax [2:0] 111 (+35.25db) set maximum gain of pga 111 = +35.25db 110 = +29.25db 101 = +23.25db 100 = +17.25db 011 = +11.25db 010 = +5.25db 001 = - 0.75db 000 = - 6.75db 8 alcsel 0 alc function select 0 = alc disabled 1 = alc enabled r33 (21h) alc control 2 3:0 alclvl [3:0] 1011 ( - 12db) alc target C
WM8950 rev 4.5 23 register address bit label default description 8 alczc 0 (zero cross off) alc uses zero cross detection circuit. 0 = disabled (recommended) 1 = enabled 7:4 alchld [3:0] 0000 (0ms) alc hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms 0011 = 10.66ms 0100 = 21.32ms 0101 = 42.64ms 0110 = 85.28ms 0111 = 0.17s 1000 = 0.34s 1001 = 0.68s 1010 or hi gher = 1.36s r34 (22h) alc control 3 8 alcmode 0 determines the alc mode of operation: 0 = alc mode (normal operation) 1 = limiter mode. 7:4 alcdcy [3:0] 0011 (26ms/6db) decay (gain ramp - up) time (alcmode ==0) per step per 6db 90% of range 0000 410us 3.38ms 23.6ms 0001 820us 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms (time doubles with every step) 0011 (5.8ms/6db) decay (gain ramp - up) time (alcmode ==1) per step per 6db 90% of range 0000 90.8us 726us 5.23ms 0001 182us 1.45ms 10.5ms 0010 363us 2.91ms 20.9ms (time doubles with every step) 3:0 alcatk [3:0] 0010 (3.3ms/6db) alc attack (gain ramp - down) time (alcmode == 0) per step per 6db 90% of range 0000 104us 832us 6ms 0001 208us 1.66ms 12ms 0010 416us 3.33ms 24ms (time doubles with every step)
WM8950 24 rev 4.5 register address bit label default description 0010 (726us/6db) alc attack (gain ramp - down) time (alcmode == 1) per step per 6db 90% of range 0000 22.7us 182.4us 1.31ms 0001 45.4us 36 3us 2.62ms 0010 90.8us 726us 5.23ms (time doubles with every step) 1010 or higher 23.2ms 186ms 1.34s table 14 alc control registers when the alc is disabled, the input pga remains at the last controlled value of the alc. a n input gain update must be made by writing to the inppgavoll/r register bits. normal mode in normal mode, the alc will attempt to maintain a constant signal level by increasing or decreasing the gain of the pga. the following diagram shows an example of this. figure 11 alc normal mode operation i n p u t s i g n a l a l c s e l p g a g a i n a l c l v l t a t k t d c y o u t p u t o f p g a v s t e p
WM8950 rev 4.5 25 limiter mode in limiter mode, the alc will reduce peaks that go above the threshold level, but will not increase the pga gain beyond the starting level. the starting level is the pga gain setting when the alc is enabled in limiter mode. if the alc is started in limiter mode, this is the gain setting of the pga at start - up. if the alc is switched into limiter mode after running in alc mode, the starting gain will be the gain at switchover. the diagram below shows an example of limiter mode. figure 12 alc limiter mode operation attack and decay tim es the attack and decay times set the update times for th e pga gain. the attack time is the time constant used when the gain is reducing. the decay time is the time constant used when the gain is increasing. in limiter mode, the time constants are faster than in alc mode. the time constants are shown below i n terms of a single gain step, a change of 6db and a change of 90% of the pgas gain range. note that, these times will vary slightly depending on the sample rate used (specified by the sr register). i n p u t s i g n a l a l c s e l p g a g a i n a l c l v l t a t k l i m t d c y l i m o u t p u t o f p g a v s t e p
WM8950 26 rev 4.5 normal mode table 15 alc normal mode (attack and decay times) limiter mode alcmode = 0 (normal mode) alcatk t atk t atk6db t atk90% 0000 104s 832s 6ms 0001 208s 1.66ms 12ms 0010 416s 3.33ms 24ms 0011 832s 6.66ms 48ms 0100 1.66ms 13.3ms 96ms 0101 3.33ms 26.6ms 192ms 0110 6.66ms 53.2ms 384ms 0111 13.3ms 106ms 767ms 1000 26.6ms 213.2ms 1.53s 1001 53.2ms 426ms 3.07s 1010 106ms 852ms 6.13s attack time (s) alcmode = 0 (normal mode) alcdcy t dcy t dcy6db t dcy90% 0000 410s 3.28ms 23.6ms 0001 820s 6.56ms 47.2ms 0010 1.64ms 13.1ms 94.5ms 0011 3.28ms 26.2ms 189ms 0100 6.56ms 52.5ms 378ms 0101 13.1ms 105ms 756ms 0110 26.2ms 210ms 1.51s 0111 52.5ms 420ms 3.02s 1000 105ms 840ms 6.05s 1001 210ms 1.68s 12.1s 1010 420ms 3.36s 24.2s decay time (s) alcmode = 1 (limiter mode) alcatk t atklim t atklim6db t atklim90% 0000 22.7s 182s 1.31ms 0001 45.4s 363s 2.62ms 0010 90.8s 726s 5.23ms 0011 182s 1.45ms 10.5ms 0100 363s 2.91ms 20.9ms 0101 726s 5.81ms 41.8ms 0110 1.45ms 11.6ms 83.7ms 0111 2.9ms 23.2ms 167ms 1000 5.81ms 46.5ms 335ms 1001 11.6ms 93ms 669ms 1010 23.2ms 186ms 1.34s attack time (s)
WM8950 rev 4.5 27 table 16 alc limiter mode (attack and decay times) minimum and maximum gain the alcmin and alcmax register bits set the minimum/maximum gain value that the pga can be set to whilst under the control of the alc. this has no effect on the pga when alc is not enabled. register address bit label default description r32 alc control 1 5:3 alcmax 111 set maximum gain of pga 2:0 alcmin 000 set minimum gain of pga table 17 alc max/min gain in normal mode, alcmax sets the maximum boost which can be applied to the signal. in limiter mode, alcmax will normally have no effect (assuming the starting gain value is less than the maximum gain specified by alcmax) because the maximum gain is set at the starting gain level. alcmin sets the minimum gain value which can be applied to the signal. figure 13 alc min/max gain alcmode = 1 (limiter mode) alcdcy t dcylim t dcylim6db t dcylim90% 0000 90.8s 726s 5.23ms 0001 182s 1.45ms 10.5ms 0010 363s 2.91ms 20.9ms 0011 726s 5.81ms 41.8ms 0100 1.45ms 11.6ms 83.7ms 0101 2.91ms 23.2ms 167ms 0110 5.81ms 46.5ms 335ms 0111 11.6ms 93ms 669ms 1000 23.2ms 186ms 1.34s 1001 46.5ms 372ms 2.68s 1010 93ms 744ms 5.36s attack time (s) p g a g a i n = 0 0 0 0 0 0 ( - 1 2 d b ) p g a g a i n = 1 1 1 1 1 1 ( + 3 5 . 2 5 d b ) a l c m a x a l c m i n a l c o p e r a t i n g r a n g e w h o l e p g a g a i n r a n g e
WM8950 28 rev 4.5 table 18 alc max gain values table 19 alc min gain values note that if the alc gain setting strays outside the alc operating range, either by starting the alc outside of the range or changing the alcmax or alcmin settings during operation, the alc will immediately adjust the gain to return to the alc operating range. it is recommended that the alc starting gain is set between the alcmax and alcmin limits. alc hold time (norma l mode only) in normal mode, the alc has an adjustable hold time which sets a time delay before the alc begins its decay phase (gain increasing). the hold time is set by the alchld register. register address bit label default description r33 alc control 2 7:4 alchld 0000 alc hold time before gain is increased. table 20 alc hold time if the hold time is exceeded this indicates that the signal h as reached a new average level and the alc will increase the gain to adjust for that new average level. if the signal goes above the threshold during the hold period, the hold phase is abandoned and the alc returns to normal operation. alcmax maximum gain (db) 111 35.25 110 29.25 101 23.25 100 17.25 011 11.25 010 5.25 001 -0.75 000 -6.75 alcmin minimum gain (db) 000 -12 001 -6 010 0 011 6 100 12 101 18 110 24 111 30
WM8950 rev 4.5 29 figure 14 alclvl i n p u t s i g n a l o u t p u t o f p g a a l c l v l p g a g a i n
WM8950 30 rev 4.5 figure 15 alc hold time table 21 alc hold time values i n p u t s i g n a l o u t p u t o f p g a a l c l v l p g a g a i n t h o l d alchld t hold (s) 0000 0 0001 2.67ms 0010 5.34ms 0011 10.7ms 0100 21.4ms 0101 42.7ms 0110 85.4ms 0111 171ms 1000 342ms 1001 684ms 1010 1.37s
WM8950 rev 4.5 31 peak limiter to prevent clipping when a large signal occurs just after a period of quiet, the alc circuit includes a limiter function. if the adc input signal exceeds 87.5% of full scale ( C 1.16db), the pga gain is ramped down at the maximum attack rate (as when alcatk = 0000), until the signal level falls below 87.5% of full scale. this function is automatically enabled whenever the alc is enabled. note: if alcatk = 0000, then the limiter makes no difference to the operation of the alc. it is designed to prevent clipping when long attack times are used. noise gate (normal m ode only) when the signal is very quiet and consists mainly of noise, the alc function may cause noise pumping, i.e. loud hissing noise during silence periods. the WM8950 has a noise gate function that prevents noise pumpin g by comparing the signal level at the input pins against a noise gate threshold, ngth. the noise gate cuts in when: signal level at adc [dbfs] < ngth [dbfs] + pga gain [db] + mic boost gain [db] this is equivalent to: signal level at input pin [dbfs] < ngth [dbfs] the pga gain is then held constant (preventing it from ramping up as it normally would when the signal is quiet). the table below summarises the noise gate control register. the ngth control bits set the noise gate threshold with respect to th e adc full - scale range. the threshold is adjusted in 6db steps. levels at the extremes of the range may cause inappropriate operation, so care should be taken with set C up of the function. the noise gate only operates in conjunction with the alc and cannot be used in limiter mode. register address bit label default description r35 (23h) alc noise gate control 2:0 ngth 000 noise gate threshold: 000 = - 39db 001 = - 45db 010 = - 51db 011 = - 57db 100 = - 63db 101 = - 69db 110 = - 75db 111 = - 81db 3 ngaten 0 nois e gate function enable 1 = enable 0 = disable table 22 alc noise gate control the diagrams below show the response of the system to the same signal with and without noise gate.
WM8950 32 rev 4.5 figure 16 alc operation a bove noise gate threshold i n p u t s i g n a l o u t p u t o f p g a a l c l v l p g a g a i n
WM8950 rev 4.5 33 figure 17 noise gate operation graphic equaliser a 5 - band graphic eq is provided, which can be applied to the adc data under control of the eqmod e register bit . register address bit label default description r 18 eq control 1 8 eqmode 1 0 = equaliser applied to adc data 1 = equaliser bypassed table 23 eq s elect the equaliser consists of low and high frequency shelving filters (band 1 and 5) and three peak filters for the centre bands. each has adjustable cut - off or centre frequency, and selectable boost (+/ - 12db in 1db steps). the peak filters have selectable bandwidth. register address bit label default description r18 eq band 1 4:0 eq1g 01100 (0db) band 1 gain control. see table 29 for details. i n p u t s i g n a l o u t p u t o f p g a a l c l v l p g a g a i n n g t h
WM8950 34 rev 4.5 register address bit label default description control 6:5 eq1c 01 band 1 cut - off frequency: 00=80hz 01=105hz 10=135hz 11=175hz table 24 eq band 1 control registe r address bit label default description r19 eq band 2 control 4:0 eq2g 01100 (0db) band 2 gain control. see table 29 for details. 6:5 eq2c 01 band 2 centre frequency: 00=230hz 01=300hz 10=385hz 11=500hz 8 eq2bw 0 band 2 band width control 0=narrow bandwidth 1=wide bandwidth table 25 eq band 2 control register address bit label default description r20 eq band 3 control 4:0 eq3g 01100 (0db) band 3 gain control. see table 29 for details. 6:5 eq3c 01 band 3 centre frequency: 00=650hz 01=850hz 10=1.1khz 11=1.4khz 8 eq3bw 0 band 3 bandwidth control 0=narrow bandwidth 1=wide bandwidth table 26 eq band 3 control register address bit label default de scription r21 eq band 4 control 4:0 eq4g 01100 (0db) band 4 gain control. see table 29 for details 6:5 eq4c 01 band 4 centre frequency: 00=1.8khz 01=2.4khz 10=3.2khz 11=4.1khz 8 eq4bw 0 band 4 bandwidth control 0=narrow band width 1=wide bandwidth table 27 eq band 4 control
WM8950 rev 4.5 35 register address bit label default description r22 eq band 5 gain control 4:0 eq5 g 01100 (0db) band 5 gain control. see table 29 for details. 6:5 eq5 c 01 band 5 cut - off frequency: 00=5.3khz 01=6.9khz 10=9khz 11=11.7khz table 28 eq band 5 control gain register gain 00000 +12db 00001 +11db 00010 +10db . (1db steps) table 29 gain register table a dedicated buffer is available for t y ing off unused analogue input pins as shown below f igure 18 . this buffer can be enabled using the bufioen register bit. f igure 18 unused input pin tie - off b uffers thermal shutdown to protect the WM8950 from overheating a thermal shutdown circuit is included. if the device tempe rature reaches approximately 125 0 c and the thermal shutd own circuit is e nabled (tsden=1 ), an interrupt can be generated . see the gpio and interrupt controller section for details. register address bit label default description r49 output c ontrol 1 tsden 1 thermal shutdown enable 0 : thermal shutdown disabled 1 : thermal shut down enabled table 30 thermal shutdown a v d d / 2 - + a v d d / 2 u s e d t o t i e o f f a l l u n u s e d i n p u t s b u f i o e n r 1 [ 2 ] 1 k m i c n 1 k m i c p 1 k a u x
WM8950 36 rev 4.5 digital audio interf ace s the audio interface has three pins: ? adcdat: adc data output ? frame : data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk, and frame can be outputs when the WM8950 operates as a master, or inputs when it is a slave (see master and s l a ve mode operation, below). five different audio data formats are supported: ? left justified ? right justified ? i 2 s ? dsp mode all of these modes are msb first. they are described in audio data formats, below. refer to the electrical characteristic section for timing information. master and slave mod e operation the WM8950 audio interf ace may be configured as e ither master or slave . as a master interface device the wm8 950 generat es bclk and frame and thus controls sequencing of the data transfer on adcdat. to set the device to master mode register bit ms should be set high. in slave mode (ms=0) , the WM8950 responds with data to clocks it receives over the digital audio interfaces. audio data formats in left justified mode, the msb is available on the first rising edge of bclk following an frame transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample r ate, there may be unused bclk cycles before each frame transition. figure 19 left justified audio interface (assuming n - bit word length) in right justified mode, the lsb is available on the last risi ng edge of bclk before a frame transition. all other bits are transmitted before (msb first). depending on word length, bclk frequency and sample rate, there may be unused bclk cycles after each frame transition. l e f t p h a s e r i g h t p h a s e f r a m e b c l k a d c d a t 1 / f s n 3 2 1 n - 2 n - 1 l s b m s b
WM8950 rev 4.5 37 figure 20 right justified audio interface (assuming n - bit word length) in i 2 s mode, the msb is available on the second rising edge of bclk following a frame transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. figure 21 i 2 s audio interface (assuming n - bit word length) in dsp/pc m mode, the left channel msb is available on the 2 nd (mode a) rising edge of bclk following a rising edge of frame. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrc output will resemble the frame pulse shown in figure 22 . in device slave mode, figure 23 it is possible to u se any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse. figure 22 dsp/pcm mode audi o interface (mode a, lrp=0, master) l e f t p h a s e r i g h t p h a s e f r a m e b c l k a d c d a t 1 / f s n 3 2 1 n - 2 n - 1 l s b m s b l e f t p h a s e r i g h t p h a s e f r a m e b c l k a d c d a t 1 / f s n 3 2 1 n - 2 n - 1 l s b m s b 1 b c l k l e f t c h a n n e l r i g h t c h a n n e l f r a m e b c l k d a c d a t / a d c d a t n 3 2 1 n - 2 n - 1 l s b m s b n 3 2 1 n - 2 n - 1 1 b c l k i n p u t w o r d l e n g t h ( w l ) 1 / f s
WM8950 38 rev 4.5 figure 23 dsp/pcm mode audio interface (mode a, lrp=0, slave) when using adclrswap = 1 in dsp/pcm mode, the data will appear in the right phase of the frame, which will be 16/20/24/32 bits after the frame pulse. register address bit label default description r4 audio interface control 1 adclrswap 0 controls whether adc data appears in right or left phases of frame clock: 0=adc data appear in left phase of 1=adc data appears in right phase of 2 s format 11= dsp /pcm mode 6:5 wl 10 word length 00=16 bits 01=20 bits 10=24 bits 11=32 bits (see note) 7 framep 0 frame clock polarity 0=normal 1=inverted dsp mode C table 31 audio interface control l e f t c h a n n e l r i g h t c h a n n e l f r a m e b c l k d a c d a t / a d c d a t n 3 2 1 n - 2 n - 1 l s b m s b n 3 2 1 n - 2 n - 1 1 b c l k i n p u t w o r d l e n g t h ( w l ) 1 / f s f a l l i n g e d g e c a n o c c u r a n y w h e r e i n t h i s a r e a 1 b c l k
WM8950 rev 4.5 39 audio interface cont rol the register bits controlling audio format, word length and master / slave mode are summarised below. each audio interface can be controlled individually. register bit ms selects audio interface operation in master or slave mode. in master mode bclk, and frame are outputs. the frequency of bclk and frame in master mode are controlled with bclkdiv . these are divided down versions of master clock . t his may result in short bclk pulses at the end of a frame if there is a non - integer ratio of bclks to frame clocks . register address bit label default description r6 cloc k g eneration c ontrol 0 ms 0 sets the chip to be master over frame and bclk 0= bclk and frame clock are input s 1= bclk and frame clock are output s generated by the WM8950 (master) 4:2 bclkdiv 0 00 configures the bclk and fram e output frequency, for use when the chip is master over bclk. 000 = divide by 1 ( bclk=mclk ) 001=divide by 2 (bclk=mclk/2) 010=divide by 4 011=divide by 8 100=divide by 16 101=divide by 32 110=reserved 111=reserved 7:5 mclkdiv 0 1 0 sets the scaling for either the mclk or pll clock output (under control of clksel) 000= divide by 1 001=divide by 1.5 010=divide by 2 011=divide by 3 100=divide by 4 101=divide by 6 110=divide by 8 111=divide by 12 8 clksel 1 controls the source of the clock for all internal operation: 0=mclk 1=pll out put tabl e 32 clock c ontrol companding the WM8950 supports a - law and ? - law companding. companding can be enabled on the adc audio interface by writing the appropriate value to the adc_comp register bit . register address bit label default description r5 companding control 2:1 adc_comp 0 adc companding 00=off 01=reserved 10= - law 11=a - law table 33 companding c ontrol
WM8950 40 rev 4.5 companding involves using a piecewise linear approximation of the following equations (as set out by itu - t g.711 standard) for data compression: ? - law (where ? =255 for the u.s. and japan): f(x) = ln(1 + ? |x|) / ln(1 + ? ) } - 1 x 1 a - law (where a=87.6 for europe): f(x) = a|x| / (1 + lna) ? for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) ? for 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for ? - law, all even data bits are inverted for a - law). the data will be transmitted as the first 8 msbs of data. companding converts 13 bits ( ? - law ) or 12 bits (a - law) to 8 bits using non - linear quantization. the input data range is separated into 8 levels, allowing low amplitude signals better precision than that of high amplitude signals. this is to exploit the operation of the human auditory sys tem, where louder sounds do not require as much resolution as quieter sounds. the companded signal is an 8 - bit word containing sign (1 - bit), exponent (3 - bits) and mantissa (4 - bits). bit 7 bit[ 6 :4] bit[3:0] sign exponent mantissa table 34 8 - bit companded word composition figure 24 u - law companding u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output
WM8950 rev 4.5 41 figure 25 a - law companding a udio s ample r ates the WM8950 sample rate for the adc is set using the sr register bits. the cut - offs for the digital filters and the alc attack/decay times stated are determined using these values and assume a 256fs master clock rate. if a sample rate that is not explicitly supported by the sr register settings is required then the closest sr value t o that sample rate should be chosen, the filter characteristics and the alc attack, decay and hold times will scale appropriately. register address bit label default description r7 additional c ontrol 3:1 sr 000 approximate sample rate (configures the co efficients for the internal digital filters) : 000=48khz 001=32khz 010=24khz 011=16khz 100=12khz 101=8khz 110 - 111=reserved table 35 sample rate control a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output
WM8950 42 rev 4.5 master clock and pha se locked loop (pll) the WM8950 has an on - chip phase - locke d loop (pll) circuit that can be used to: generate master clocks for the WM8950 audio functions from another external clock, e.g. in telecoms applications. generate and output (on pin csb /gpio) a clock for another part of the system that is derived from an existing audio master clock. figure 26 shows the pll and internal clocking arrang e ment on the WM8950 . the pll can be enabled or disabled by the pllen register bit. register address bit label default description r1 power management 1 5 pllen 0 pll enable 0=pll off 1=pll on table 36 pllen c ontrol b it figure 26 pll and clock select circuit the pll frequency ratio r = f 2 /f 1 (see figure 26 ) can be set using the register bits pllk and plln: plln = int r pllk = int (2 24 (r - plln)) example: mclk=12mhz, required clock = 12.288mhz. r should be chosen to ensure 5 < plln < 13. there is a fixed divide by 4 in the pll and a selectable divide by n after the pll which should be set to divide by 2 to meet this requirement. enabling the divide by 2 sets the required f 2 = 4 x 2 x 12.288mhz = 98.304mhz. r = 98.304 / 12 = 8.192 plln = int r = 8 k = int ( 2 24 x (8.192 C 8)) = 32212 25 = 3126e9 h m c l k f / 2 p l l 1 r = f 2 / f 1 f / 4 2 5 6 f s c s b / g p i o f 2 f 1 g p i o s e l r 8 [ 2 : 1 ] . . . p l l p r e s c a l e r 3 6 [ 4 ] f / n m c l k d i v r 6 [ 7 : 5 ] o p c l k d i v r 8 [ 5 : 4 ] f / n a d c f / 4 m a s t e r m o d e a d c o s r 1 2 8 r 1 4 [ 3 ] f r a m e b c l k c l k s e l r 6 [ 8 ] f / 2 b c l k d i v r 6 [ 4 : 2 ] m s r 6 [ 0 ] m s r 6 [ 0 ] f p l l o u t
WM8950 rev 4.5 43 register address bit label default description r36 pll n value 4 pllprescale 0 0 = mclk input not divided (default) 1 = divide mclk by 2 before input to pll 3:0 plln 10 00 integer (n) part of pll input/output frequency ratio. use values grea ter than 5 and less than 13. r37 pll k value 1 5:0 pllk [23:18] 0ch fractional (k) part of pll1 input/output frequency ratio (treat as one 24 - digit binary number). r38 pll k value 2 8:0 pllk [17:9] 093 h r39 pll k value 3 8:0 pllk [8:0] 0e9 h table 37 pll frequency ratio control the pll performs best when f 2 is around 90mhz. its stability peaks at n=8. some exam ple settings are shown in figure 35 . mclk (mhz) (f1) desired output (mhz) f2 (mhz) prescale d ivide postscale divide r n (hex) k (hex) 12 11.2896 90.3168 1 2 7.5264 7 86c220 12 12.288 98.304 1 2 8.192 8 3126e8 13 11.2896 90.3168 1 2 6.947446 6 f28bd4 13 12.288 98.304 1 2 7.561846 7 8fd525 14.4 11.2896 90.3168 1 2 6.272 6 45a1ca 14.4 12.288 98 .304 1 2 6.826667 6 d3a06e 19.2 11.2896 90.3168 2 2 9.408 9 6872af 19.2 12.288 98.304 2 2 10.24 a 3d70a3 19.68 11.2896 90.3168 2 2 9.178537 9 2db492 19.68 12.288 98.304 2 2 9.990243 9 fd809f 19.8 11.2896 90.3168 2 2 9.122909 9 1f76f7 19.8 12.288 98.3 04 2 2 9.929697 9 ee009e 24 11.2896 90.3168 2 2 7.5264 7 86c226 24 12.288 98.304 2 2 8.192 8 3126e8 26 11.2896 90.3168 2 2 6.947446 6 f28bd4 26 12.288 98.304 2 2 7.561846 7 8fd525 27 11.2896 90.3168 2 2 6.690133 6 boac93 27 12.288 98.304 2 2 7.281778 7 482296 table 38 pll frequency examples
WM8950 44 rev 4.5 general purpose inpu t/output the csb /gpio pin can b e configured to perform a variety of useful tasks by setting the gpiosel register bits. the gpio is only available in 2 wire mode. regi ster address bit label default description r8 gpio c ontrol 2:0 gpiosel 000 csb /gpio pin function select: 000= csb input 001= reserved 010=temp ok 011=a uto mute active 100=pll clk o/p 101=pll lock 110=reserved 111=reserved 3 gpiopol 0 gpio polarity invert 0 =non inverted 1=inverted 5:4 opclkdiv 00 pll output clock division ratio 00=divide by 1 01=divide by 2 10=divide by 3 11=divide by 4 table 39 csb /gpio control control interface selection of control mode and 2 - wire mode address the control interface can operate as either a 3 - wire or 2 - wire mpu interface. the mode pin determines the 2 or 3 wire mode as shown in table 40 . the WM8950 is controlled by writing to registers through a serial control interface. a control word consists of 16 bits. the first 7 bits (b15 to b9) are address bits that select which control register is accessed. the remaining 9 bits (b8 to b0) are register bits, corresponding to the 9 bits in each control register. mode interface format low 2 wire high 3 wire table 40 control interface mode selection 3 - wire serial control mode in 3 - wire mode, every rising edge of sclk clocks in one data bit from the s din pin. a rising edge on csb/gpio latches in a complete con trol word consisting of the last 16 bits. figure 27 3 - wire serial control interface b 1 5 b 1 4 b 1 3 b 1 2 b 1 1 b 1 0 b 9 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 s d i n s c l k c s b c o n t r o l r e g i s t e r a d d r e s s c o n t r o l r e g i s t e r d a t a b i t s l a t c h
WM8950 rev 4.5 45 2 - wire serial control mode the WM8950 supports software control via a 2 - wire serial bus. many devices can be contro lled by the same bus, and each device has a unique 7 - bit device address (this is not the same as the 7 - bit address of each register in the WM8950 ). the WM8950 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sdin while sclk remains high. this indicates that a device address and data will follow. all devices on the 2 - wire bus respond to the start condition and shift in the next eight bits on sdin (7 - bit address + read/write bit, msb first) . if the device address received matches the address of the WM8950 , then the WM8950 responds by pulling sdin low on the next clock pulse (ack). if the address is not recognised or the r/w bit is 1 when operating in write only mode, the WM8950 returns to the idle condition and wait for a new start condition and valid address. during a write, once the WM8950 has acknowledged a correct address, the controller sends the first byte of control data (b15 to b8, i.e. the WM8950 register address plus the first bit of register data). the WM8950 then acknowledges the first data byte by pulling sdin low for one clock pulse. the controller then sends the second byte of control data (b7 to b0, i.e. the remaining 8 bits of register data), and the WM8950 acknowledges agai n by pulling sdin low. transfers are complete when there is a low to high transition on sdin while sclk is high. after a complete sequence the WM8950 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sdin changes while sclk is high), the device jumps to the idle condition. figure 28 2 - wire serial control interface in 2 - wire mode t he WM8950 has a fixed device addre ss, 0 011010 . r esetting the chip the WM8950 can be reset by performing a write of any value to the software reset register (address 0 hex). this will cause all register values to be reset to their default values. in addition to this there is a power - on reset (por) circuit which ensures that the registers are set to default when the device is powered up. sdin sclk register address and 1st register data bit device address (7 bits) rd / wr bit ack (low) control byte 1 (bits 15 to 8) control byte 1 (bits 7 to 0) remaining 8 bits of register data stop start ack (low) ack (low)
WM8950 46 rev 4.5 power supplies the WM8950 can use up to three separate power supplies: avdd , avdd2, agnd and agnd 2 : analogue supply, powers all analogue functions. avdd can r ange from 2.5v to 3.6v and has the most significant impact on overall power consumption. a large avdd s lightly improves audio quality. dcvdd: digital core supply, powers all digital functions except the audio and control int er faces. dcvdd can range from 1. 71v to 3.6v, and has no effect on audio quality. the return path for dcvdd is dgnd, which is shared with dbvdd. dbvdd can ra n ge from 1. 71 v to 3.6v. dbvdd return path is through dgnd. it is possible to use the same supply voltage for all supplies . however, digital and analogue supplies should be routed and decoupled separately on the pcb to keep digital switching noise out of the analogue signal paths. adc power up/down se quence figure 29 adc power up a nd down sequence (not to scale) symbol min typical max unit t midrail_on 500 ms t midrail_off >10 s t adcint 2/fs n /fs table 41 typical por operation (typical values, not tested) notes: v p o r a d g n d i n t e r n a l p o r a c t i v e d e v i c e r e a d y n o p o w e r v p o r _ o f f p o w e r s u p p l y p o r i 2 s c l o c k s a d c i n t e r n a l s t a t e t m i d r a i l _ o n a n a l o g u e i n p u t s a d c d a t p i n g d a d c e n b i t p o w e r d o w n i n i t n o r m a l o p e r a t i o n n o r m a l o p e r a t i o n i n i t p d p o w e r d o w n a d c e n a b l e d a d c e n a b l e d a d c o f f t a d c i n t d n c i n p p g a e n b i t t a d c i n t i n p p g a e n a b l e d d n c g d g d g d p o r p o r u n d e f i n e d v m i d e n a b l e d v m i d s e l / b i a s e n b i t s a v d d / 2 t m i d r a i l _ o f f ( n o t e 1 ) ( n o t e 2 ) ( n o t e 3 ) ( n o t e 4 ) v p o r _ o n
WM8950 rev 4.5 47 1. the analogue input pin charge time, t midrail_on, is determined by the vmid pin charge time. this time is dependent upon the value of vmid decoupling capacitor and vmid pin input resistance and avdd power supply rise time. 2. the analogue input pin discharge time, t midrail_off, is determined by the analogue input coupling capacitor discharge time. the time, t midrail_off , is measured using a 1 f capacitor on the analogue input but will vary dependent upon the value of input coupling capacitor. 3. while the adc is enabled there will be lsb data bit activity on the adcdat pin due to system noise but no significant digital output will be present. 4. the vmidsel and biasen bits must be set to enable analogue input midrail voltage and for normal adc operation. 5. adcdat data output delay from power up - with p ower supplies starting from 0v - is determined primarily by the vmid charge time. adc initialisation and power management bits may be set immediately after por is released; vmid charge time will be significantly longer and will dictate when the device is s tabilised for analogue input. 6. adcdat data output delay at power up from device standby (power supplies already applied) is determined by a dc initialisation time, 2/fs. p ower m anagement saving power by redu cing oversampling ra te the default mode of operat ion of the adc digital filters is in 64x oversampling mode. under the control of adcosr the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device . register address bit label default description r14 adc control 3 adcosr 128 0 adc oversample rate select 0 = 64x (lowest power) 1 = 128x (best snr) table 42 adc oversampling rate selection vmid the analogue circuitry will not work unless vmid is enabled (vmidsel 00). the impedance of the vmid resistor string, together with the decoupling capacitor on the vmid pin will determine the start - up time of the vmid circuit. register address bit label default description r1 power management 1 1:0 vmidsel 00 reference string impedance to vmid pin (dete r mines start - up time): 00 = off (open circuit) 01 = 50k ? ? ? table 43 vmid i mpedance c ontrol biasen register address bit label default description r1 power managem ent 1 3 biasen 0 analogue amplifier bias control table 44 biasen control
WM8950 48 rev 4.5 estimated supply cur rents when the adc is enabled it is estimated that approximately 4ma will be drawn from dcvdd when dcvdd=1.8v and fs=48khz . (this will be lower at lower sample rates). when the pll is enabled an additional 700 microamps will be drawn from dcvdd. table 59 shows the estimated 3.3v avdd current drawn by various circuits, by register bit. register bit avdd current (millia mps) pllen 1.4 (with clocks applied) micben 0.5 biasen 0.3 bufioen 0.1 vmidsel 10k=>0.3, less than 0.1 for 5 0k/500k inppgaen 0.2 adcen x64 (adcosr=0)=>2.6, x128 (adcosr=1)=>4.9 table 45 avdd supply current
WM8950 rev 4.5 49 r egister m ap addr b[15:9] register nam e b8 b7 b6 b5 b4 b3 b2 b1 b0 def t val dec hex (hex) 0 00 software reset software reset 1 01 power m anaget 1 0 0 auxen pllen micben biasen bufioen vmidsel 000 2 02 power m anaget 2 0 0 0 0 boosten 0 inppgaen 0 adcen 000 4 04 audio interfac e bcp framep wl fmt 0 alrswap 0 0 50 5 05 companding ctrl 0 0 0 0 0 adc_comp 0 000 6 06 clock gen ctrl clksel mclkdiv bclkdiv 0 ms 140 7 07 additional ctrl 0 0 0 0 0 sr slowclk en 000 8 08 gpio stuff 0 0 0 opclkdiv gpiopol gpiosel 000 14 0e adc control hpfen hpfapp hpfcut adcosr 128 0 0 adcpol 10 0 15 0f adc digital vol 0 adcvol 0ff 18 12 eq1 C low shelf 0 0 eq1c eq1g 12c 19 13 eq2 C peak 1 eq2bw 0 eq2c eq2g 02c 20 14 eq3 C peak 2 eq3bw 0 eq3c eq3g 02c 21 15 eq4 C peak 3 eq4bw 0 eq4c eq4g 02c 22 16 eq5 C high shelf 0 0 eq5c eq5g 02c 27 1b notch filter 1 nfu nfen nfa0[13:7] 000 28 1c notch filter 2 nfu 0 nfa0[6:0] 000 29 1d notch filter 3 nfu 0 nfa1[13:7] 000 30 1e notch filter 4 nfu 0 nfa1[6:0] 000 32 20 alc control 1 alcsel 0 0 alcmax alcmin 03 8 33 21 alc control 2 alczc alchld alclvl 00b 34 22 alc control 3 alcmode alcdcy alcatk 032 35 23 noise gate 0 0 0 0 0 ngen ngth 000 36 24 pll n 0 0 0 0 pll_pre scale plln[3:0] 00 8 37 25 pll k 1 0 0 0 pllk[23:18] 00c 38 26 pll k 2 pllk[17:9] 093 39 27 pll k 3 pllk[8:0] 0e9 44 2c input ctrl mbvsel 0 0 0 0 auxmode aux2 inppga micn2 inppga micp2 inppga 003 45 2d inp pga gain ctrl 0 inppgazc inppga mute inppgavol 0 1 0 47 2f adc boost ctrl pgaboost 0 micp2boostvol 0 aux2boostvol 100 49 31 thermal shut down 0 0 0 0 0 0 0 tsden 0 002
WM8950 50 rev 4.5 digital filter chara cteristics parameter test conditions min typ max unit adc filter passband +/ - 0.0 2 5db 0 0.4 54 fs - 6db 0.5fs passband ripple +/ - 0.0 2 5 db stopband 0.5 46 fs stopband attenuation f > 0.546 fs - 60 db group delay 21 /fs adc high - pass filter high - pass filter corner frequency - 3db 3.7 hz - 0.5db 10.4 - 0.1db 21.6 table 46 digital filter characteristics terminology 1. stop band attenuation (db) C the degre e to which the frequency spectrum is attenuated (outside audio band) 2. pass - band ripple C any variation of the frequency response in the pass - band region 3. note that this delay applies only to the filters and does not include additional delays through other di gital circuits. see table 47 for the total delay. parameter test conditions min typ max unit adc path group delay total delay (adc analogue input to digital audio interface output) eq disabled 26/fs 28/fs 30/fs eq enabled 27 /fs 29/fs 31/fs table 47 total group delay note : wind noise filter is disabled. adc filter responses figure 30 adc digital filter frequency response figure 31 adc digital filter ripple -120 -100 -80 -60 -40 -20 0 0 0.5 1 1.5 2 2.5 3 frequency (fs) response (db) -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 0.1 0.2 0.3 0.4 0.5 frequency (fs) response (db)
WM8950 rev 4.5 51 de - emphasis filter resp onses figure 32 de - emphasis frequency response (32khz) figure 33 de - emphasis error (32khz) figure 34 de - emphasis frequency re sponse (44.1khz) figure 35 de - emphasis error (44.1khz) figure 36 de - emphasis frequency response (48khz) figure 37 de - emphasis error (48khz) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 2000 4000 6000 8000 10000 12000 14000 16000 frequency (hz) response (db) -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 2000 4000 6000 8000 10000 12000 14000 16000 frequency (hz) response (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) response (db) -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0 5000 10000 15000 20000 frequency (hz) response (db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) response (db) -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0 5000 10000 15000 20000 frequency (hz) response (db)
WM8950 52 rev 4.5 high - pass filter the wm89 50 has a selectable digital high - pass filter in the adc filter path. this filter has two modes, audio and applications. in audio mode the filter is a 1 st order iir with a cut - off of around 3.7hz. in applications mode the filter is a 2 nd order high - pass filter with a selectable cut - off frequency. figure 38 adc high - pass filter response, hpfapp=0 figure 39 adc high - pass filter responses (48khz), hpfapp=1, all cut - off settings shown. figure 40 adc high - pass filter responses (24khz), hpfapp=1, all cut - off settings shown. figure 41 adc high - pass filter responses (12khz), hpfapp=1, all cut - off settings shown. -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 5 10 15 20 25 30 35 40 45 frequency (hz) response (db) -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10 0 200 400 600 800 1000 1200 frequency (hz) response (db)
WM8950 rev 4.5 53 5 - band equaliser the WM8950 has a 5 - band equalise r which can be applied to the adc path. the plots from figure 42 to figure 55 show the frequency responses of each filter with a sampling frequency of 48khz, firstly showing the different cut - off/centre frequencies with a gain of ? 12db, and secondly a sweep of the gain from - 12db to +12db for the lowest cut - off/centre frequency of each filter. figure 42 eq b and 1 C low frequency s helf f ilter c ut - offs figure 43 eq b and 1 C g ains for l owest c ut - off f requency figure 44 eq b and 2 C peak f ilter c entre f requencies , eq2bw=0 figure 45 eq b and 2 C peak f ilter g ains fo r l owest c ut - off f requency, eq2bw=0 figure 46 eq b and 2 C eq2bw=0, eq2bw=1 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db)
WM8950 54 rev 4.5 figure 47 eq b and 3 C peak f ilter c entre f requencies, eq3bw=0 figure 48 eq b and 3 C pea k f ilter g ains for l owest c ut - off f requency, eq3bw=0 figure 49 eq b and 3 C eq3bw=0, eq3bw=1 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db)
WM8950 rev 4.5 55 figure 50 eq b and 4 C peak f ilter c entre f requencies, eq3bw=0 figure 51 eq b and 4 C peak f ilter g ains for l owest c ut - off f requency, eq4bw=0 figure 52 eq b and 4 C eq3bw=0, eq3bw=1 figure 53 eq b and 5 C high frequency s helf f ilter c ut - offs figure 54 eq b and 5 C g ains for l owest c ut - off f requency 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -2 10 -1 10 0 10 1 10 2 10 3 10 4 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db) 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 frequency (hz) magnitude (db)
WM8950 56 rev 4.5 figure 55 shows the result of having the gain set on more than one channel simultaneously. the blue traces show each band (lowest cut - off /centre frequency) with ? 12db gain. the red traces show the cumulative effect of all bands with +12db gain and all bands - 12db gain, with eqxbw=0 for the peak filters. figure 55 cumulative f requency b oost/ c ut 10 -1 10 0 10 1 10 2 10 3 10 4 10 5 -15 -10 -5 0 5 10 15 20 frequency (hz) magnitude (db)
WM8950 rev 4.5 57 a pplications information recommended external components figure 56 recommended e xternal components w m 8 9 5 0 d n c d n c d n c t p a v d d 2 a g n d 2 n o t e s : 1 . a g n d a n d d g n d s h o u l d b e c o n n e c t e d a s c l o s e t o t h e w m 8 9 5 0 a s p o s s i b l e . 2 . c 1 , c 2 , c 3 , c 4 , c 8 a n d c 9 s h o u l d b e p o s i t i o n e d a s c l o s e t o w m 8 9 5 0 a s p o s s i b l e . 3 . c a p a c i t o r t y p e s s h o u l d b e c a r e f u l l y c h o s e n . c a p a c i t o r s w i t h v e r y l o w e s r a r e r e c o m m e n d e d f o r o p t i m u m p e r f o r m a n c e . 4 . r 3 c a n b e p o p u l a t e d w i t h o t h e r v a l u e s t o r e m o v e c o m m o n m o d e n o i s e o n t h e m i c r o p h o n e . 5 . f o r a d d e d s t r e n g t h a n d h e a t d i s s i p a t i o n , i t i s r e c o m m e n d e d t h a t t h e g n d _ p a d d l e ( p i n 2 5 ) i s c o n n e c t e d t o a g n d . a v d d d c v d d d b v d d a d c d a t f r a m e b c l k m c l k a u x v m i d m i c b i a s m i c p m i c n g n d _ p a d d l e s d i n s c l k c s b / g p i o m o d e d g n d a g n d
WM8950 58 rev 4.5 package diagram dm 102 . c fl : 24 pin qfn plastic package 4 x 4 x 0 . 9 mm body , 0 . 50 mm lead pitch index area ( d / 2 x e / 2 ) top view d e 4 notes : 1 . dimension b applies to metallized terminal and is measured between 0 . 15 mm and 0 . 30 mm from terminal tip . 2 . falls within jedec , mo - 220 , variation vggd - 8 . 3 . all dimensions are in millimetres . 4 . the terminal # 1 identifier and terminal numbering convention shall conform to jedec 95 - 1 spp - 002 . 5 . coplanarity applies to the exposed heat sink slug as well as the terminals . 6 . refer to applications note wan _ 0118 for further information regarding pcb footprints and qfn package soldering . 7 . this drawing is subject to change without notice . a 3 g t h w b exposed lead half etch tie bar dimensions ( mm ) symbols min nom max note a a 1 a 3 0 . 80 0 . 85 0 . 90 0 . 05 0 . 0 35 0 0 . 20 3 ref b d d 2 e e 2 e l 0 . 30 0 . 20 4 . 00 bsc 2 . 60 2 . 50 2 . 40 0 . 50 bsc 0 . 3 5 0 . 40 0 . 45 2 2 4 . 00 bsc 2 . 60 2 . 50 2 . 40 0 . 10 aaa bbb ccc ref : 0 . 1 0 0 . 10 jedec , mo - 220 , variation vggd - 8 . tolerances of form and position 0 . 25 h 0 . 1 0 0 . 2 0 g t 0 . 1 03 w 0 . 15 detail 1 detail 3 6 1 13 18 24 19 12 e d 2 b 7 1 b c bbb m a bottom view c aaa 2 x c aaa 2 x 1 c a 3 seating plane a 1 c 0 . 08 c ccc a 5 side view exposed ground paddle 6 detail 1 0 . 30 mm 45 exposed ground paddle e 2 see detail 2 l e datum detail 2 terminal tip e / 2 1 m m detail 3
WM8950 rev 4.5 59 important notice contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com. for the purposes of our terms and conditions of sale, "preliminary" or "advanced" datashee ts are non - final datasheets that include but are not limited to datasheets marked as target, advance, product preview, preliminary technical data and/or pre - production. products provided with any such datasheet are therefore subject to relevant t erms and conditions associated with "preliminary" or "advanced" designations. the products and services of cirrus logic international (uk) limited; cirrus logic, inc.; and other companies in the cirrus logic group (collectively either cirrus logic or ci rrus) are sold subject to cirrus logics terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. software is provided pursuant to applicable license t erms. cirrus logic reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from cirrus logic to verify that the information is current and complete. testing and other quality control techniques are utilized to the extent cirrus logic deems necessary. specific testing of all parameters of each device is not necessarily performed. in order to minimize risks associ ated with customer applications, the customer must use adequate design and operating safeguards to minimize inherent or procedural hazards. cirrus logic is not liable for applications assistance or customer product design. the customer is solely responsibl e for its selection and use of cirrus logic products. use of cirrus logic products may entail a choice between many different modes of operation, some or all of which may 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WM8950 60 rev 4.5 revision history date rev originator changes 26/09/11 4.4 jmacd order codes changed from WM8950gefl/v and WM8950gefl/rv to WM8950cgefl/v and WM8950cgefl/rv to reflect change to copper wire bond ing. 26/09/11 4.4 jmacd package diagram ch anged to dm102. c 1 2 /08/16 4.5 ph micbias voltage (mbvsel=1) updated to 0.75 x avdd. system clock timing requirements updated.

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